Power converters are widely used in a range of electronic and electro-mechanical systems to efficiently process and deliver energy where the energy source may supply power at one voltage level and the load requires a substantially different voltage level. Efficient power converters use switching techniques and energy storage components such as capacitors or inductors to transform voltage and current levels to the levels required by the load. For example, a microprocessor may operate at 1 V and 100 A, but the system power bus or battery provides a 12 V supply. A power converter, in this case a DC-DC converter, is needed to transform the 12 V supply to a 1 V supply that can be used by the microprocessor.
Conventional ‘Switched Capacitor (hereinafter “SC”) converters are well known in the art]. Resonant switched capacitor (hereinafter “ReSC”) converters have similarities to SC converters in terms of the applicable architectures, but are less well known in the art. Typically, SC and ReSC converters operate only with fixed conversion ratios (for example ½, 2, ⅔, 3, etc) when operating efficiently.
FIG. 1 shows a prior art behavioral model 100 of SC and ReSC converters considering only DC operation. The converters can be modeled as an ideal transformer that converts voltage VIN to substantially VOUT=VIN*M, where M is defined here as the ideal conversion ratio of the converter (M is shown represented by the turns ratio of an equivalent transformer model). By the power conservation of the transformer model, the input and output currents are also scaled by the conversion ratio such that IIN is substantially IIN=M*IOUT. The parameter REFF in FIG. 1 represents the effective output resistance of the converter. Details of calculating REFF for SC converters are provided in H. Le, S. R. Sanders, E. Alon, “Design Techniques for Fully Integrated Switched-Capacitor DC-DC converters,” IEEE J. Solid-State Circuits, 2011, vol. 46, no. 9, pp. 2120-2131 (attached hereto as Appendix A). Details of calculating REFF for ReSC converters are provided in K. Kesarwani, R. Sangwan, and J. T. Stauth, “Resonant Switched-Capacitor Converters for Chip-Scale Power Delivery: Modeling and Design,” IEEE Workshop on Control and Modeling for Power Electronics (COMPEL), 2013 (attached hereto as Appendix B). It is typically desirable to have lower REFF as this implies lower conduction losses in the circuit and that the conversion ratio will be closer to the ideal conversion ratio when the load is drawing substantial current. Here, therefore, we will define the ideal conversion ratio as M=VOUT/VIN for the case where REFF is substantially zero or IIN=M*IOUT is substantially zero.
SC DC-DC converters have gained prominence in recent years due to several favorable characteristics. One advantage of SC converters is that they provide better utilization of semiconductor switching devices (such as MOSFETS) compared to inductor-based topologies (such as buck or boost converters). This is especially true in situations where the ratio of the supply voltage to the required output voltage (the conversion ratio) is high. Specifically, the advantage of SC topologies is the ability to operate with lower conduction loss (power loss that occurs due to the flow of electrical current) for a given voltage-current (V-A) current rating of the power devices.
Additional trends that favor SC converters are the inherently higher energy-density (defined as the maximum energy storage a component can achieve divided by the component's area or volume) of capacitors compared to inductors in many voltage and current ranges. The energy-density of capacitors that can be integrated using currently available semiconductor micro-fabrication techniques is considerably higher than can be achieved using integrated inductors and other magnetic components. Also, new micro-fabrication techniques have enabled much higher energy density for capacitors compared to what was available in traditional semiconductor processes.
In the prior art, methods have been described to adjust the output voltage of SC circuits by adjusting the effective output resistance, REFF, of the SC converter. For example in the SC converter, the switching frequency can be reduced to increase output resistance. Therefore, at a fixed load current, higher resistance will reduce the output voltage consistent with the resistive load line of the converter. However, this mode of regulation is inherently inefficient, much like a linear regulator. Also, this method can only adjust the output voltage down from a nominal conversion ratio.
ReSC converters have several advantages compared to SC converters. ReSC converters utilize magnetic energy storage to resonate out the reactive impedance of capacitor energy storage devices. This enables them to operate at lower switching frequencies while still achieving comparable conduction loss. Operating at lower switching frequencies reduces frequency-dependent losses such as power required to turn semiconductor switches on and off, and bottom-plate switching losses. FIG. 2 depicts prior art a graph 200 comparing REFF normalized to the parasitic effective series resistance, RESR, of both SC 202 and ReSC 204 converters versus frequency. In both cases, the same total capacitance is used, and the converters operate with the same RESR. Several major features are seen: 1) both SC and ReSC converters have REFF that varies with frequency, 2) the ReSC converter can achieve nearly the same REFF, but at a lower (resonant) frequency, 3) in both converters the minimum REFF is limited by RESR.
FIG. 3 depicts a representative prior art SC converter 300 configured to provide an ideal conversion ratio of ½ between the supply, VIN 302, and output, VOUT 304. FIG. 4 depicts a representative prior art ReSC converter 400 configured to provide an ideal conversion ratio of ½ between the supply, VIN 402, and output, VOUT 404. The ReSC circuit 400 of FIG. 4 includes four switching devices (418, 420, 422, and 424) each controlled by a respective one of clock signals clk1-clk4 (410, 412, 414, 416, respectively). In normal operation of ReSC 400, resonant impedance Zx 408, including capacitance Cx 406 and inductance Lx 426, are configured in parallel with VIN−VOUT for a first time interval, T1. In interval T1, Cx 406 and Zx 408 store energy derived from supply VIN 402. In a second time interval, T2, Cx 406 and Zx 408 are configured in parallel with VOUT 404, delivering energy to the load that is connected between VOUT 404 and GND 409. SC 300 operates in a similar manner without having impedance Zx 408.
Alternatively, as discussed in Stauth et al U.S. Pat. Nos. 8,390,147 and 8,384,245, an energy source or load may be configured in parallel with each bypass capacitor. In this case the SC or ReSC converter can be used to balance the power flow in each energy source or load. FIG. 5 shows a prior art example 500 where energy elements E1 and E2 develop voltages V1 and V2 and are stacked in series. VT represents the total series voltage of the stack referenced to ground and is where the total energy provided or sourced from the stack is delivered to or drawn from. FIG. 6 shows a prior art hierarchical example 600 of N−1 converters configured in parallel with N energy elements to balance the power flow among the energy elements.
FIG. 7 shows waveforms for normal operation of the ReSC converter 400 of FIG. 4. In time interval T1 702, clk3 (414) and clk4 (416) are high. Signals clk1 (410) and clk2 (412) are synchronous with clk3 (414) and clk4 (416) respectively, but transition between VOUT 404 and VIN 402. In time interval T1, Zx 408 is configured in parallel with VIN 402 and VOUT 404 such that Vx=VIN−VOUT. In time interval T2 704, Zx 408 is configured in parallel with VOUT 404 such that Vx=VOUT. If VIN−VOUT is not equal to VOUT 404, Vx is a voltage square wave at a frequency set by T1 702 and T2 704. The frequency of the square wave is substantially fsw=1/(T1+T2). Normally fsw is substantially equal to a resonant frequency of Zx, f0. If Zx is a second-order series L-C circuit, then f0 is substantially 1/2π√{square root over (LxCx)} for the fundamental resonant frequency. It can be seen in FIG. 2 that fsw could also be an integer subharmonic of f0, but that this would result in higher REFF than operation at f0. Normally T1=T2 such that the duty cycle, D, defined as D=T1/(T1+T2) is substantially 0.5. In this case, in time interval T1 702, the current, Ix, through Zx 408 is substantially a positive half-wave rectified sinusoid. This current flows to increase the energy stored in Cx 406. In time interval T2 704, the voltage across Zx 408 is VOUT 404. A negative half-wave rectified sinusoid flows in Zx 408 which transfers energy to VOUT 404.
The magnitude of the square wave of voltage that is applied across Zx 408 is related to the amount of current drawn from VOUT 404 by the load. The low frequency or time-averaged behavior can be modeled by effective resistance REFF, as shown in FIG. 2. The conversion ratio for ideal operation, defined as operation when REFF is substantially zero, is ½ for the convertor 400 of FIG. 4. VOUT 404 may be less than VIN/2 due to the load current flowing through REFF.
The above described waveforms in FIG. 7 may additionally apply to the configurations in FIGS. 5 and 6 except that the voltage Vx would transition between V1 and V2 or V2 and V1 instead of VIN−VOUT and VOUT.